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real-time clock rp/ rf/ rs5c62 electronic devices division no.ea-012-9803 application manual
no tice 1. the products and the product specifications described in this application manual are subject to change or dis - continuation of production without notice for reasons such as improvement. therefore, before deciding to use the products, please refer to ricoh sales representatives for the latest information thereon. 2. this application manual may not be copied or otherwise reproduced in whole or in part without prior written con - sent of ricoh. 3. please be sure to take any necessary formalities under relevant laws or regulations before exporting or other - wise taking out of your country the products or the technical information described herein. 4. the technical information described in this application manual shows typical characteristics of and example application circuits for the products. the release of such information is not to be construed as a warranty of or a grant of license under ricoh's or any third party's intellectual property rights or any other rights. 5. the products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. we are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. in order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. we do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. anti-radiation design is not implemented in the products described in this application manual. 8. please contact ricoh sales representatives should you have any questions or comments concerning the prod - ucts or the technical information. june 1995
outline ...................................................................................................... 1 fea tures .................................................................................................... 1 block dia gram ......................................................................................... 1 pin configura tion ................................................................................... 2 pin description ........................................................................................ 2 absolute maximum ra tings ................................................................... 3 recommended opera ting condition .................................................... 3 dc electrical chara cteristics ........................................................... 4 a c electrical chara cteristics ........................................................... 5 timing char t ............................................................................................. 5 functional description ......................................................................... 6 1. addressing ................................................................................................. 6 2. functions of registers ................................................................................... 7 3. functions of counters .................................................................................. 15 usa ge ........................................................................................................ 17 1. reading and wr iting oper ations ...................................................................... 17 2. handling of ce pin ...................................................................................... 18 3. configur ation of oscillator y circuit .................................................................... 19 4. adjustment of oscillation f requencies ............................................................... 20 5. interr upts ................................................................................................. 22 6. timer ...................................................................................................... 23 7. detection of stop of oscillation ........................................................................ 24 8. t ypical p o w er supply circuit ........................................................................... 25 9. t ypical connection betw een rp/rf/rs5c62 and cpu ........................................... 26 10. t ypical char acter istics .................................................................................. 27 11. t ypical softw are-controlled processes ............................................................... 29 rp / rf / rs5c62 applica tion manu al contents
q uestions and answers on use ......................................................... 34 p a cka ge dimensions .............................................................................. 42 t aping specifica tions ........................................................................... 43
real-time clock 1 rp/rf/rs5c62 outline the rp/rf/rs5c62 are cmos lsis which serve microcomputers as real-time clocks providing time, calendar, and alarm functions in direct coupling with the data buses of cpus such as 8086 and 68000. a built-in timer counter acts as a watchdog timer or interrupt timer. they are available in three different types of packages: the dip type, the sop type, and the ssop type. ?directly connected to cpu, enabling fast access. ?4bit bidirectional data bus, and 4bit address bus. ?the oscillator is driven by a constant voltage, so the oscillation frequency is stable even when the power supply voltage fluctuates. ?built-in timer counter using internal clock. ?generates cyclic cpu interrupts, and generates alarm-match interrupts. ?interrupt flag and interrupt inhibit. ?clock (hour, minute, second), calendar (leap year, year, month, day, day-of-the-week), alarm (hour, minute). ?12-or 24-hour mode is selectable. ?recognizes leap years automatically. ?all clock and alarm data expressed in bcd codes. ? 30 seconds adjustment function. ?determines whether clock data is valid or invalid. ?consumes very low power due to cmos technology, so it can be backed up by batteries. ?power supply voltage between 3.0 to 5.0v. ?time keeping supply voltage between 2.0 to 6.0v. ?package : 18pin dip for RP5C62, 18pin sop for rf5c62, 20pin ssop for rs5c62. fea tures block dia gram i n t e r r u r t c o n t r o l t i m e r c o n t r o l r e g i s t e r a d d r e s s b u s c o n t r o l d a t a b u s c o n t r o l d 0 d 1 d 2 d i v o s c d e t e c t o s c o s c i n o s c o u t c e d 3 a 0 a 1 a 2 a 3 a d d r e s s d e c o d e r a l a r m r e g i s t e r c o m p a r a t o r w a t c h & c a l e n d a r v d d v s s t m o u t c s r d w r i n t r
function cs and ce are used when interfacing external devices. they may be accessed when cs is low and ce is high. ce is connected to an output of power down detector on the system power supply side, and cs is connected to the microcom - puter address bus. timer output may be used as an interrupt free-run timer or watchdog timer. when ce is low (running on battery backup), operation stops (there is no output). it is n-ch open drain output. address input is connected to the cpu address bus. it is gated internally with ce. when rd falls from high to low, the contents of the counters or registers specified by a0 to a3 are output to d0 to d3. it is valid when cs is low and ce is high. it is cmos input. when wr falls from high to low or rises from low to high, the contents of d0 to d3 are written to registers or counters specified by a0 to a3. wr is valid when cs is low and ce is high. it is cmos input. d0 to d3 are connected to the cpu data bus. the input section is gated internally with ce. it is cmos input/output. intr outputs cyclic interrupts or alarm interrupts to cpu. it also operates when ce is low (at battery backup). it is n-ch open drain output. crystal oscillator of 32.768khz must be connected between oscin and oscout. capacitance is connected externally between v dd and oscin and v dd and oscout, forming the oscillator circuit. v dd connects to +5v or +3v and v ss to ground. 2 pin configura tion rp/rf/rs5c62 v d d v d d o s c o u t o s c o u t o s c i n o s c i n d 3 d 2 d 1 d 0 i n t r w r c s c e t m o u t a 1 a 2 a 3 r d a 0 v s s 1 2 3 5 6 7 8 4 9 1 8 1 7 1 6 1 4 1 3 1 2 1 1 1 5 1 0 i n t r d 3 d 2 d 1 d 0 w r c e a 0 a 1 a 2 a 3 v s s 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 2 3 4 5 6 7 8 9 c s t m o u t r d v d d o s c o u t o s c i n n c i n t r d 3 d 2 d 1 d 0 w r c s c e t m o u t n c a 0 a 1 a 2 a 3 r d v s s 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 2 3 4 5 6 7 8 9 1 0 pin description pin no. symbol name 1 cs chip select input 2 ce chip enable input 3 tmout timer output 4 ? a 0 ?3 address input 8 rd read control input 10 wr write control input 11?4 d 0 ?3 bi-directional data bus 15 intr interrupt output 16 oscin oscillator circuit 17 oscout input/output 18 v dd 9 v ss power supply * ) the pin numbers marked in the above table indicate the pins on the 18pin packages. ?RP5C62 (18pin dip) ?rf5c62 (18pin sop) ?rs5c62 (20pin ssop)
3 rp/rf/rs5c62 absolute maximum ra tings recommended opera ting condition absolute maximum ratings v ss =0v symbol item conditions ratings unit v dd supply voltage ?.3 to +7.0 v v i input voltage ?.3 to +v dd +0.3 v v o output voltage 1 intr, tmout ?.3 to +12.0 v output voltage 2 except intr, tmout ?.3 to +v dd +0.3 v p d maximum power dissipation ta=25?c 300 mw topt operating temperature ?0 to +70 ?c tstg storage temperature ?0 to +125 ?c v ss =0v, topt=?0 to +70?c symbol item conditions limits unit min. typ. max. v dd supply voltage 2.7 5.0 6.0 v v clk time keeping supply voltage 2.0 6.0 v f xt crystal oscillation frequency 32.768 khz v pup pull-up voltage for intr, tmout pin intr, tmout 10 v absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such values for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degradation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits.
4 dc electrical chara cteristics rp/rf/rs5c62 unless noted, v ss =0v, v dd =5v 10%, topt=?0 to +70?c, x'tal=32.768khz, (r 1 2 35k ? ), c g =10pf, c d =10pf symbol item pin name conditions limits unit min. typ. max. v ih1 ??input voltage a0 to a3, d0 to d3 2.2 v dd +0.3 v v il1 ??input voltage cs, rd, wr ?.3 0.8 v v ih2 ??input voltage ce 0. 8 v dd v dd +0.3 v v il2 ??input voltage ?.3 0.2 v dd v v oh1 ??output voltage d0 to d3 i oh1 =?00 a 2.4 v v ol1 ??output voltage i ol1 =2ma 0.4 v v ol2 ??output voltage intr, tmout i ol2 =2ma 0.4 v i ilk input leak current a0 to a3, ce, v ilk =v dd or v ss ? 1 a cs, rd, wr i oz1 output off leak d0 to d3 v oz1 =v dd or v ss ? 5 a i oz2 current intr, tmout v oz2 =v dd ? 2 a i oz3 intr, tmout v oz3 =10v ? 5 a i dd1 consumption v dd v dd =2.5v, ce=l 3 a current for back-up others : open consumption v dd =5.5v, ce=h, cs=h, i dd2 current for stand-by v dd output : open 8 a input : v dd or v ss ? f oscillation frequency oscin v dd =2.5 to 5.5v ? 1 ppm drift for voltage drift oscout topt=25?c
5 rp/rf/rs5c62 a c electrical chara cteristics timing char t v ss =0v, topt=?0 to +70?c symbol item v dd = 5v 10% v dd = 3v 10% v dd = 5v 20% unit min. max. min. max. min. max. t ces ce setup time 500 1,000 500 ns t ceh ce hold time 500 1,000 500 ns t as (rd) address setup time (for read) 20 20 20 ns t as (wr) address setup time (for write) 20 20 20 ns t ah (rd) address hold time (for read) 10 10 10 ns t ah (wr) address hold time (for write) 10 10 10 ns t rr output data delay time (c l =100pf) 120 295 150 ns t rz output data floating time 70 95 75 ns t w write pulse width 120 195 150 ns t ds input data setup time 60 95 75 ns t dh input data hold time 10 10 10 ns r e a d c e o r o r a 0 t o a 3 d 0 t o d 3 ( r e a d d a t a ) d 0 t o d 3 ( w r i t e d a t a ) w r i t e c s r d r d c s c s w r w r c s t c e s t c e h t d h v a l i d v a l i d t r r t a h ( r d ) t a s ( r d ) t a s ( w r ) t a h ( w r ) t r z t d s t w * ) the diagonally shaded sections marked in the above timing chart indicate the allowable high or low levels of the cs, rd, an d wr pin inputs. input/output conditions (v d d = 5v 10%) (v d d = 3 v 10%) (v d d = 5v 20%) v i h = 2.2v v i h = 0.8 v dd v i h = 2.4v v i l = 0.8v v i l = 0.2 v dd v i l = 0.4v v o h = 2.2v v o h = 0.8 v dd v o h = 2.4v v o l = 0.8v v ol = 0.2 v dd v o l = 0.4v
6 rp/rf/rs5c62 functional description 1. ad dressing address bus bank 0 (bank=0) bank 1 (bank=1) a3 a2 a1 a0 description d3 d2 d1 d0 description d3 d2 d1 d0 0 0 0 0 0 1 sec. counter r/w s 8 s 4 s 2 s 1 cyclic interrupt select reg. w/o ct 3 ct 2 ct 1 ct 0 1 0 0 0 1 10 sec. counter r/w s 40 s 20 s 10 adust reg. w/o adj 2 0 0 1 0 1 min. counter r/w m 8 m 4 m 2 m 1 1 min. alarm reg. r/w am 8 am 4 am 2 am 1 3 0 0 1 1 10 min. counter r/w m 40 m 20 m 10 10 min. alarm reg. r/w am 40 am 20 am 10 4 0 1 0 0 1 hour counter r/w h 8 h 4 h 2 h 1 1 hour alarm reg. r/w ah 8 ah 4 ah 2 ah 1 5 0 1 0 1 10 hour counter r/w p/a h 10 10 hour alarm reg. r/w ap/a ah 10 or h 20 or ah 20 6 0 1 1 0 day-of-the-week counter r/w w 4 w 2 w 1 7 0 1 1 1 1 day counter r/w d 8 d 4 d 2 d 1 8 1 0 0 0 10 day counter r/w d 20 d 10 9 1 0 0 1 1 month counter r/w mo 8 mo 4 mo 2 mo 1 a 1 0 1 0 10 month counter r/w mo 10 12/24 select reg. w/o 12/24 b 1 0 1 1 1 year counter r/w y 8 y 4 y 2 y 1 leap year reg. r/o ly 1 ly 0 r/w lye w/o tm 2 tm 1 tm 0 c 1 1 0 0 10 year counter r/w y 80 y 40 y 20 y 10 timer clock select reg. r/w tm 3 r/o tmfg d 1 1 0 1 control reg. 1 w/o wten alen tmr bank control reg. 1 w/o wten alen tmr bank e 1 1 1 0 control reg. 2 r/o bsy control reg. 2 r/o bsy r/w ctfg alfg xstp r/w ctfg alfg xstp f 1 1 1 1 control reg. 3 w/o tsta tstb wtrst control reg. 3 w/o tsta tstb wtrst * 1) r/w bits can be read and written. r/o bits can only be read. w/o bits can only be written. * 2) it is no problem to attempt writing to r/o bits and blank bits, but the attempt will fail. * 3) if w/o bits and blank bits are read, the returned value is 0. * 4) the control registers 1, 2, and 3 have the same address assignment for bank0 and bank1.
7 rp/rf/rs5c62 2. functions of register s 2.1 contr ol register 1 (bank0/1 at ?h? d 3 d 2 d 1 d 0 0 0 0 0 w t e n a l e n t m r b a n k ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) * 1 b a n k s w i t c h i n g b i t b a n k f u n c t i o n 0 1 s p e c i f i e s s e l e c t i o n o f b a n k 0 i n t h e a d d r e s s t a b l e . s p e c i f i e s s e l e c t i o n o f b a n k 1 i n t h e a d d r e s s t a b l e . t m r f u n c t i o n 0 1 s p e c i f i e s n o c h a n g e . s p e c i f i e s r e s e t t i n g o f t h e t i m e r c o n d i t i o n a l o n r e s t a r t . t i m e r r e s e t t i n g b i t * 2 a l e n f u n c t i o n 0 1 d i s a b l e s a n a l a r m i n t e r r u p t . e n a b l e s a n a l a r m i n t e r r u p t . a l a r m o p e r a t i o n s e t t i n g b i t * 3 w t e n f u n c t i o n 0 1 d i s a b l e s a c a r r y t o t h e 1 - s e c o n d t i m e d i g i t . e n a b l e s a c a r r y t o t h e 1 - s e c o n d t i m e d i g i t . t i m e c o u n t o p e r a t i o n s e t t i n g b i t * 4 * 1) the bank bit is intended for only write operation and always read as ?? * 2) the timer frequency can be set by the timer clock selection register. * 3) setting the alen bit to ??during output of an alarm interrupt from the intr pin (while it is held low) turns off the int r pin. setting the alen bit to ??in matching between clock time and alarm time drives the intr pin low within a maximum of 61.1 s. * 4) a 1-second carry with the wten bit set to ??increments the second digit by 1 upon setting of the wten bit to ?? this bit will automatically be set to ??upon driving low the ce pin.
8 rp/rf/rs5c62 2.2 contr ol register 2 (b ank0/1 at ?h? d 3 d 2 d 1 d 0 b s y c t f g a l f g x s t p c t f g a l f g x s t p ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) x s t p f u n c t i o n 0 1 i n d i c a t e s t h e p r o g r e s s o f o s c i l l a t i o n . i n t e n d e d f o r s e t t i n g t o 0 . i n d i c a t e s t h e s t o p o f o s c i l l a t i o n . n o t i n t e n d e d f o r s e t t i n g t o 1 . a l f g f u n c t i o n 0 1 i n d i c a t e s a n a l a r m i n t e r r u p t i s d i s a b l e d o r i n d i c a t e s m i s m a t c h i n g b e t w e e n c l o c k t i m e a n d a l a r m t i m e ( u p o n t u r n i n g o f f t h e i n t r p i n ) . i n t e n d e d f o r s e t t i n g t o 0 . i n d i c a t e s m a t c h i n g b e t w e e n c l o c k t i m e a n d a l a r m t i m e ( u p o n d r i v i n g l o w t h e i n t r p i n ) . n o t i n t e n d e d f o r s e t t i n g t o 0 . a l a r m t i m e m a t c h i n d i c a t i o n b i t * 3 c t f g f u n c t i o n 0 1 i n d i c a t e s t h a t t h e i n t r p i n i s t u r n e d o f f . i n t e n d e d f o r s e t t i n g t o 0 i n t h e l e v e l m o d e . i n d i c a t e s t h a t t h e i n t r p i n i s d r i v e n l o w . n o t i n t e n d e d f o r s e t t i n g t o 0 . c y c l i c i n t e r r u p t i n d i c a t i o n b i t * 4 b s y f u n c t i o n 0 1 i n d i c a t e s t h e n o r m a l s t a t e o f t h e t i m e a n d c a l e n d a r c o u n t e r s ( n o c a r r y o r n o r e s e t p u l s e ) . i n d i c a t e s t h e b u s y s t a t e o f t h e t i m e a n d c a l e n d a r c o u n t e r s ( a c a r r y o r a r e s e t p u l s e g e n e r a t e d ) . t i m e / c a l e n d a r c o u n t e r s t a t e i n d i c a t i o n b i t * 5 * * 1 o s c i l l a t i o n s t o p d e t e c t i o n b i t * 2 * 1) the bsy bit is intended for only read operation and is not intended for write operation. * 2) the xstp bit is used to detect the stop of the crystal oscillator. the xstp bit is set to ??upon the stop of oscillatio n and held at ??after the restart of oscillation. upon detection of the stop of oscillation, the built-in timer counter is reset (because the tm 3 bit in the timer clock selection register is reset). * 3) when the alen bit is set to ?? the alfg bit is also set to ??upon output of an alarm interrupt from the intr pin (whil e it is held low).
9 rp/rf/rs5c62 * 4) the ctfg bit is set to ??upon output of a cyclic interrupt from the intr pin (while it is held low). (a cyclic interrupt may occur in the pulse mode and the level mode.) a l f g i n t r a l a r m t i m e m a t c h a l a r m t i m e m a t c h s e t t i n g t h e a l f g b i t t o 0 a l a r m t i m e m a t c h c t f g i n t r c t f g i n t r i n t e r r u p t p r e s e t i n t e r r u p t c y c l e s e t t i n g t h e c t f g b i t t o 0 i n t e r r u p t * 5) when the bsy bit is set to ?? write operation must not be performed upon the time and calendar counters which are being updated. normally, read operation must be performed from the counters upon setting the bsy bit to ?? reading from them without checking the bsy bit requires separate software for preventing reading errors. the bsy bit is set to ??in the four cases below: s e t t i n g t h e a d j b i t t o 1 s e t t i n g t h e w t e n b i t t o 1 s e t t i n g t h e w t r s t b i t t o 1 c o m p l e t i o n o f r e s e t c o m p l e t i o n o f p u l s e f o r c a r r y t o s e c o n d d i g i t c o m p l e t i o n o f c o r r e c t i o n b y + 1 c o m p l e t i o n o f a d j u s t m e n t m a x . 1 2 2 . 1 s m a x . 1 2 2 . 1 s m a x . 1 2 2 . 1 s 3 0 . 5 s 9 1 . 6 s ?pulse mode (the ct 3 bit is set to ??) (the ctfg bit is not intended for write operation.) ?level mode (the ct 3 bit is set to ??) (the ctfg bit is intended for setting to ? only.) (i) adjustment by 30 seconds (ii) correction by +1 (when there is a 1-second carry in transition of the wten bit fro m ??t o ?? (iii) normal 1-second carry (iv) counter resetting (setting of wtrst bit) (resetting the 1 to 8hz dividers)
10 rp/rf/rs5c62 2.3 contr ol register 3 (b ank0/1 at ?h? d 3 d 2 d 1 d 0 0 0 0 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) * 2 b i t f o r r e s e t t i n g l o w e r - o r d e r c o u n t e r t h a n t h e s e c o n d c o u n t e r . * 3 w t r s t f u n c t i o n 0 1 s p e c i f i e s n o r m a l o p e r a t i o n . s p e c i f i e s r e s e t t i n g o f 1 - t o 8 - h z d i v i d e r s c o n d i t i o n a l o n r e s t a r t . t s t a , t s t b f u n c t i o n 0 1 s p e c i f i e s s e t t i n g o f t h e t e s t m o d e . s p e c i f i e s s e t t i n g o f n o r m a l o p e r a t i o n . t e s t m o d e s e t t i n g b i t s * 4 t s t a t s t b w t r s t * * 1 * 1) the bit marked with * ?is not intended for write operation. * 2) this bit is intended for only write operation and always read as ?? * 3) when set to ?? the wtrst bit specifies resetting of the lower-order counter than the 1 second counter ranging from 8hz a nd 4hz to 2hz and 1hz conditional on restart. the wtrst bit is used to adjust the lower-order counter than the 1 second counter. after the wtrst bi t is set to ?? the bsy bit is set to ??for a maximum of 122. 1 s. * 4) both the tsta and tstb bits must be set to ? to specify normal operation and will automatically be set to ??upon driving low the ce pin. 2.4 adjustment register (b ank1 at ?h? d 3 d 2 d 1 d 0 0 0 0 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) * 2 s e c o n d d i g i t a d j u s t m e n t b i t * 3 f u n c t i o n 0 1 s p e c i f i e s n o r m a l o p e r a t i o n . s p e c i f i e s a d j u s t m e n t o f s e c o n d d i g i t . * * 1 * * a d j a d j * 1) the bits marked with * ?are not intended for write operation. * 2) this bit is intended for only write operation and always read as ?? * 3) the adj bit is used to correct the second digit. when set to ?? the adj bit functions as follows: 1) for digits ranging from 00 seconds to 29 seconds ? resets the lower-order counter than the 1 second counter (in the same manner as the wtrst bit) and sets the second digit to ?0? 2) for digits ranging from 30 seconds to 59 seconds ? resets the second and lower-order counters (in the same manner as the wtrst bit), sets the second digit to ?0?and increments the minute digit by 1. the bsy bit is set to ??for a maximum of 122.1 s after the adj bit is set to ??
11 rp/rf/rs5c62 2.5 interrupt cyc le selection register (b ank1 at ?h? d 3 d 2 d 1 d 0 0 0 0 0 c t 3 c t 2 c t 1 c t 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) * 1 i n t e r r u p t c y c l e / o u t p u t m o d e s e l e c t i o n b i t s * 2 * 1) these bits are intended for only write operation and always read as ?? * 2) the ct 3 to ct 0 bits are used to set interrupt cycles and output modes as shown in the table below: * ) the bits marked with * ?are set to ??or ?? c t f g p r e s e t i n t e r r u p t c y c l e i n t r c t f g i n t r i n t e r r u p t s e t t i n g t h e c t f g b i t t o 0 ( i n t e r r u p t ) ?pulse mode (the ct 3 bit is set to ??) (the ctfg bit is not intended for write operation.) ?level mode (the ct 3 bit is set to ??) (the ctfg bit is intended for setting to ??only.) ct3 ct2 ct1 ct0 intr remarks * 0 0 0 ?ff disable a cyclic interrupt. * 0 0 1 2048hz specify a cycle (t) of 0.488ms (1/2048hz). * 0 1 0 1024hz specify a cycle (t) of 0.977ms (1/1024hz). * 0 1 1 128hz specify a cycle (t) of 7.813ms (1/128hz). * 1 0 0 16hz specify a cycle (t) of 62.5ms (1/16hz). * 1 0 1 1hz specify a cycle (t) of 1s (1/1hz). * 1 1 0 1/60hz specify a cycle (t) of 60s (1/1/60hz). * 1 1 1 ?n specify the fixed low level of the intr pin output. 0 * * * pulse mode specify a duty cycle of 50%. see below. 1 * * * level mode see below. ?relationship between intr pin output and upward second count i n t r i n t r u p w a r d s e c o n d c o u n t u p w a r d s e c o n d c o u n t u p w a r d s e c o n d c o u n t u p w a r d s e c o n d c o u n t ( 1 ) p u l s e m o d e ( w h e n 1 h z o r 1 / 6 0 h z i s s e l e c t e d ) ( 2 ) l e v e l m o d e ( w h e n 1 h z o r 1 / 6 0 h z i s s e l e c t e d ) 3 0 . 5 s 3 0 . 5 s
d3 d2 d1 d0 am 8 am 4 am 2 am 1 (for read and write operations) 1-minute alarm digit (a t ?h? * am 40 am 20 am 10 (for read and write operations) 10-minute alarm digit (a t ?h? ah 8 ah 4 ah 2 ah 1 (for read and write operations) 1-hour alarm digit (a t ?h? * * ap/a or ah 20 ah 10 (for read and write operations) 10-hour alarm digit (a t ?h? 12 rp/rf/rs5c62 2.6 alarm register (1-min ute , 10-min ute , 1-hour , and 10-hour) (b ank1 at ?h to 5h? * 1) the bits marked with * are always read as ??and not intended for write operation. * 2) when enabling an alarm interrupt, non-existent minute and hour alarm digits must not be left (to prevent mismatching betwe en clock time and alarm time). * 3) alarm minute and hour settings are exemplified in the table below: * 4) in the the 12-hour time scale, the hour digits of 12 and 32 indicate 0 o'clock a.m. and 0 o'clock p.m., respectively. alarm minute 12-hour time scale 24-hour time scale and hour setting 10-hour 1-hour 10-minute 1-minute 10-hour 1-hour 10-minute 1-minute digit digit digit digit digit digit digit digit 0 : 00 a.m. 1 2 0 0 0 0 0 0 1 : 30 a.m. 0 1 3 0 0 1 3 0 1 1 : 59 a.m. 1 1 5 9 1 1 5 9 0 : 00 p.m. 3 2 0 0 1 2 0 0 1 : 30 p.m. 2 1 3 0 1 3 3 0 1 1 : 59 p.m. 3 1 5 9 2 3 5 9 2.7 12/24-hour time scale selection register (b ank1 at ?h? d 3 d 2 d 1 d 0 0 0 0 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) * 2 1 2 / 2 4 - h o u r t i m e s c a l e s e l e c t i o n b i t * 3 , 4 f u n c t i o n 0 1 s e l e c t s t h e 1 2 - h o u r t i m e s c a l e w i t h a . m . a n d p . m . i n d i c a t i o n s . s e l e c t s t h e 2 4 - h o u r t i m e s c a l e . * * 1 * * 1 2 / 2 4 1 2 / 2 4 * 1) the bits marked with * ?are not intended for write operation. * 2) these bits are intended for only write operation and always read as ?? * 3) the time digits are indicated in binary-coded decimal (bcd) notation as shown in the table below:
13 rp/rf/rs5c62 * 4) the 12-hour or 24-hour time scale must be selected before time of day adjustment or alarm time setting (e.g. at the time of initialization after power-on from 0v) d 3 d 2 d 1 d 0 0 l y 1 l y 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) ( l y 1 , l y 0 ) f u n c t i o n ( 0 , 0 ) a n y o t h e r v a l u e s p e c i f i e s l e a p y e a r i n d i c a t i o n ( i n c l u d i n g f e b r u a r y 2 9 ) ( w h e n t h e l y e b i t i s s e t t o 0 . s p e c i f i e s n o r m a l y e a r i n d i c a t i o n ( n o t i n c l u d i n g f e b r u a r y 2 9 ) . * * 1 * * l e a p y e a r i n d i c a t i o n b i t s ( i n t e n d e d f o r o n l y r e a d o p e r a t i o n ) * 2 f u n c t i o n 0 1 e n a b l e s l e a p y e a r i n d i c a t i o n . d i s a b l e s l e a p y e a r i n d i c a t i o n . l e a p y e a r i n d i c a t i o n s e l e c t i o n b i t * 3 , 4 l y e l y e l y e 2.8 leap y ear indication register (b ank1 at ?h? 24-hour time scale 12-hour time scale 12-hour time scale 24-hour time scale 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) * 1) the bits marked with * ?are not intended for write operation. * 2) the ly1 and ly0 bits cycle from ?0?via ?1?and ?0?to ?1?with the passage of years. * 3) upon setting the lye bit to ?? automatic correction is made for leap years in the years 1901 to 2099 (e.g. 1992, 1996, a nd 2000). upon setting the lye bit to ?? leap year indication is disabled (counting up to february 28). * 4) writing to the 1-year or 10-year counter enables leap year indication (sets the lye bit to ??.
14 rp/rf/rs5c62 * 1) only the tm 3 bit is intended for read operation. the d0 bit is always read as ?mfg? the d2 and d1 bits are always read as ?? * 2) the tm 3 to tm 0 bits are used to set cycles for the counters as shown in the table below. 2.9 timer cloc k selection register (b ank1 at ?h? d 3 d 2 d 1 d 0 0 0 t m f g t m 3 t m 3 t m 2 t m 1 t m 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) * 1 t i m e r c o u n t e r c y c l e s e t t i n g b i t ( t m 3 t o t m 0 ) * 2 t i m e r o u t p u t i n d i c a t i o n b i t ( t m f g ) * 3 t1 : maximum time during which timer output is disabled after timer resetting. (timer reset occurs upon setting the tmr bit to ??in the control register 1.) (timer output occurs upon driving low the tmout pin output.) t2 : time between timer output and cycle setting during timer resetting (upon setting the tm 3 bit to ??), or timer resetting, or transition of the ce pin input from its low to high levels. t3 : timer output cycle without timer reset. tm 3 tm 2 tm 1 tm 0 t1 t2 t3 (watchdog timer cycle) (output time after timer resetting) (free-running timer cycle) 0 * * * timer output disabled timer output disabled timer output disabled (tmout pin output turned off) (tmout pin output turned off) (tmout pin output turned off) 1 0 0 0 562ms 562 to 626ms 625ms 1 0 0 1 281ms 281 to 313ms 312.5ms 1 0 1 0 140ms 140 to 157ms 156.3ms 1 0 1 1 70.3ms 70.3 to 78.2ms 78.13ms 1 1 0 0 35.1ms 35.1 to 39.1ms 39.06ms 1 1 0 1 17.5ms 17.5 to 19.6ms 19.53ms 1 1 1 0 8.78ms 8.78 to 9.77ms 9.766ms 1 1 1 1 4.39ms 4.39 to 4.89ms 4.883ms
d3 d2 d1 d0 s 8 s 4 s 2 s 1 (for read and write operations) 1-second time digit (a t ?h? * s 40 s 20 s 10 (for read and write operations) 10-second time digit (a t ?h? m 8 m 4 m 2 m 1 (for read and write operations) 1-minute time digit (a t ?h? * m 40 m 20 m 10 (for read and write operations) 10-minute time digit (a t ?h? h 8 h 4 h 2 h 1 (for read and write operations) 1-hour time digit (a t ?h? * * p/a or h 20 h 10 (for read and write operations) 10-hour time digit (a t ?h? 15 rp/rf/rs5c62 * 3) relationship between tmfg bit and tmout pin output * 4) the timer is stopped (the tmout pin output is turned off) upon driving low the ce pin input, but restarted upon driving hi gh the ce pin input. * 5) timer output is disabled (the tmout pin output is turned off) upon resetting the tm 3 bit to ??when the stop of oscillation is detected (setting the xstp bit to ??. * 6) timer output is turned off (the tmout pin output is turned off) upon setting the tmr bit to ??in the control register 1 during timer output (while the tmout pin is held low). * 1) the bits marked with * ?are always read as ??and not intended for write operation. * 2) upon setting the wten bit to ??in the control register 1, a carry to the 1-second time digit from the second counter is disabled. * 3) the time digits are indicated in bcd notation as shown below: second digit: ranges from 00 to 59 and carried to the minute digit in transition from 59 to 00. minute digit: ranges from 00 to 59 and carried to the hour digit in transition from 59 to 00. hour digit: ranges as shown in ?. 7 12/24-hour time scale selection register?and carried to the day or day-of-the-week digi t in transition from 11 p.m. to 12 a.m. or from 23 to 00. * 4) a carry from any non-existent time digit must be avoided because it may cause malfunction in the time counter. t m o u t t m f g s e t t i n g t h e t m r b i t t o 1 s e t t i n g t h e t m r b i t t o 1 0 . 2 4 4 m s m a x . t 1 t 2 t 3 3. functions of counter s 3.1 time counter (b ank0 at ?h to 5h?
d3 d2 d1 d0 d 8 d 4 d 2 d 1 (for read and write operations) 1-day calendar digit (a t ?h? * * 1 * d 20 d 10 (for read and write operations) 10-day calendar digit (a t ?h? mo 8 mo 4 mo 2 mo 1 (for read and write operations) 1-month calendar digit (a t ?h? * * * mo 10 (for read and write operations) 10-month calendar digit (a t ?h? y 8 y 4 y 2 y 1 (for read and write operations) 1-year calendar digit (a t ?h? y 80 y 40 y 20 y 10 (for read and write operations) 10-year calendar digit (a t ?h? d3 d2 d1 d0 * w 4 w 2 w 1 (for read and write operations) day-of-the-week counter 16 rp/rf/rs5c62 * 1) the bits marked with * ?are always read as ??and not intended for write operation. * 2) the day-of-the-week counter is incremented by 1 in a carry to the 1-day calendar digit. * 3) days of the week written to the w 4 , w 2 , and w 1 bits are counted up in septimal notation as shown below : (000) ? (001) ? ..... ? (110) ? (000) the correspondence between days of the week and readings of the day-of-the-week counter is user-definable (e.g. sunday=000) * 4) the w 4 , w 2 , and w 1 bits must not be all set to 1. 3.2 da y-of-the-week counter (b ank0 at ?h? 3.3 calendar counter (b ank0 at ?h?to ?h? * 1) the bits marked with * ?are always read as ??and not intended for write operation. * 2) the calendar digits are indicated in bcd notation by the automatic calendar function as shown below: day digi t : ranges from 1 to 31 (in january, march, may, july, august, october, and december) ranges from 1 to 30 (in april, june, september, and november) ranges from 1 to 29 (in february in leap years) ranges from 1 to 28 (in february in normal years) carried to the month digit in transition back to 1. month digi t : ranges from 1 to 12 carried to the year digit in transition back to 1. year digi t : ranges from 00 to 99 including leap years of 00, 04, 08, - - - - - -, 92, and 96 (when leap year indication is enabled by setti ng the lye bit in the leap year indication register to ??). * 3) a carry from any non-existent calendar digit must be avoided because it may cause malfunction in the calendar counter.
17 rp/rf/rs5c62 usa ge 1. reading and writing operations c e a d d r e s s r e a d i n g o p e r a t i o n w r i t i n g o p e r a t i o n d a t a b u s a 3 t o a 0 d 3 t o d 0 c s w r r d upon driving high the ce pin, the interfacing input/out - put pins are enabled, establishing equivalence in logic between the rd and cs pin inputs during read opera - tion and between the wr and cs pin inputs during write operation. upon driving low the ce pin, the inter - facing input/output pins are disabled, preventing occur - rence of invalid leak current due to their floating. the ce pin must always be driven either high or low and must never be left floating. 1.1 reading operation the requirements for reading data from the internal registers and counters are: [1] holding the ce pin high, [2] performing the process of addressing through the a3 to a0 pin inputs, then [3] driving low the cs pin, [4] causing the rd pin to transition from its high to low levels, and thereby [5] causing the d3 to d0 pins to output read data. the reading timing is shown in the chart below. c e a 0 t o a 3 d 0 t o d 3 ( r e a d d a t a ) t c e h t c e s v a l i d t a h ( r d ) t a s ( r d ) t r z t r r o r c s r d r d c s [ 1 ] [ 2 ] [ 3 ] [ 4 ] [ 5 ] * 1) the cs and rd pin inputs are interchangeable. the diagonally shaded sections marked in the above timing chart may be set to both high and low levels. (consequently, the cs and rd pin inputs may be caused to transition from their high to low levels before the process o f addressing.) * 2) t as (rd)?indicates the time required to perform the process of addressing before the start of read operation at which both the rd and cs pin inputs are driven low. * 3) t ah (rd)?ndicates the time required to maintain the result of addressing after the completion of read operation at which either th e rd or cs pin input is driven high.
18 rp/rf/rs5c62 1.2 writing operation the requirements for writing data to the internal registers and counters are: [1] holding the ce pin high, [2] per - forming the process of addressing through the a3 to a0 pin inputs, then [3] driving low the cs pin, [4] causing the wr pin to transition from its high to low to high levels, and thereby [5] causing the d3 to d0 pins to input data to be written. the writing timing is shown in the chart below. c e a 0 t o a 3 d 0 t o d 3 ( w r i t e d a t a ) t c e h t c e s v a l i d t a h ( w r ) t a s ( w r ) t d h t d s o r c s w r w r c s t w [ 1 ] [ 2 ] [ 3 ] [ 4 ] [ 5 ] * 1) the cs and wr pin inputs are interchangeable. the diagonally shaded sections marked in the above timing chart may be set to both high and low levels. (consequently, the cs and wr pin inputs may be caused to transition from their high to low levels before the process o f addressing.) * 2) t as (wr)?indicates the time required to perform the process of addressing before the start of write operation at which both the wr and cs pin inputs are driven low. * 3) t ah (wr)?indicates the time required to maintain the result of addressing after the completion of write operation at which either the wr or cs pin input is driven high. * ) the ce pin must be driven as low as the v ss pin whenever possible in order to minimize battery consumption in battery backup (while the ce pin is held low). 2. handling of ce pin normally, the ce pin is connected to the supply voltage detection circuit of the system power supply. in switch - ing the system power supply (see the typical power supply circuit), the ce pin must be driven low before the voltage across the system power supply drops below the lower limit to the operating voltage of the cpu (at the point ( [1 ] ) in the timing chart below) and then driven high after the supply voltage rises above the lower limit to the operating voltage of the cpu (at the point ( [2 ] ) in the timing chart below). c e v d d l o w e r l i m i t t o o p e r a t i n g v o l t a g e o f c p u b a t t e r y v o l t a g e 0 . 2 v d d 0 . 2 v d d m i n . 0 s m i n . 0 s v o l t a g e a c r o s s s y s t e m p o w e r s u p p l y [ 1 ] [ 2 ]
19 rp/rf/rs5c62 3. configuration of oscillator y cir cuit v d d v d d o s c o u t o s c i n c g 3 2 k h z c d r p / r f / r s 5 c 6 2 r f r d a typical external components: x'tal : 32.768 khz r 1 2 35k ? c g =5pf to 35pf c d =5pf to 35pf standard values of internal elements: r f =12m ? r d =60k ? in the oscillatory circuit, which is driven by a constant voltage of about 2v relative to the vdd pin, either one end of the oscillatory capacitors c g and c d must be connected to the vdd pin without exception. reference < considerations in installing components surrounding oscillatory circuit > < other relevant considerations > when either one end of the oscillatory capacitors c g and c d is connected to the vss pin instead of the vdd pin, the oscillatory circuit is still operational but subject directly to fluctuations in the voltage of the system power supply. under sharp fluctuations between 5v and battery voltage in particular, the oscillatory circuit may be brought to a temporary stop. thus, it is not recommendable to connect either one end of the oscilla - tory capacitors c g and c d to the vss pin. 1) install the oscillatory capacitors c g and c d in the closest possible proximity to the ic. 2) avoid laying any signal or power line in the proximity of the oscillatory circuit (particularly in the area marked with ? a ? ? in the above figure). 3) apply the highest possible insulation resistance between the oscin or oscout pin and the printed cir - cuit board (pcb). 4) avoid using any long parallel line to wire the oscin and oscout pin. 5) take extreme care not to cause condensation, which leads to various problems such as failure of the crys - tal oscillators. 1) when applying an external input of clock pulses (32.768khz) to the oscin pin: dc coupling ........... prohibited due to mismatching input levels. ac coupling ........... permissible except that unpredictable results may occur upon detection of the stop of oscillation if any error occurs in such detection due to such factors as noises. timer operation is prohibit - ed upon detection of the stop of oscillation. 2) avoid using the oscillator output of the rp/rf/rs5c62 (from the oscout pin) to drive any other ic for the purpose of ensuring stable oscillation characteristics.
20 rp/rf/rs5c62 4. adjustment of oscillation frequencies 4.1 measurement of oscillation frequenc y the oscillation frequency can be measured by using the intr pin output (a cyclic interrupt). note that its mea - surement is affected by and cannot therefore be obtained with accuracy by the oscin pin input and the oscout pin output, which are directly measured by such means as a probe. f r e q u e n c y c o u n t e r v d d v d d * 3 * 2 * 1 o s c o u t o s c i n c d c g i n t r * 1) use a frequency counter with 6 or more readout digits in order to ensure an accuracy on the order of 1ppm. * 2) pull up the intr pin to the v dd and set the ce pin to high. * 3) connect either one end of the oscillatory capacitors c g and c d to the v dd pin. p o w e r - o n f r o m 0 v * 4 * 5 * 6 * 7 * 8 i n t e r r u p t c y c l e s e l e c t i o n r e g i s t e r r e a d f r e q u e n c y c o u n t e r c o n t r o l r e g i s t e r 3 c h c o n t r o l r e g i s t e r 1 1 h c o n t r o l r e g i s t e r 2 0 h 5 h * 4) set both the tsta and tstb bits to ??in the control register 3 to disable the test circuit. * 5) set the alen bit to ??and the bank bit to ??in the control register 1 to disable an alarm interrupt. * 6) set both the ctfg and alfg bits to ??in the control register 2 to disable an alarm interrupt and a cyclic interrupt. * 7) set a cyclic interrupt to 1hz (or any other cycle) in the pulse mode. * 8) an error of 1ppm for every 1hz amounts to a time lag of approximately 2.6 seconds per month. [example of monthly time lag calculation given an error of 1ppm for every 1hz. 1ppm x 60 seconds x 60 minutes x 24 hours x 30 days = 2.592 = approx. 2.6 seconds per month ]
21 rp/rf/rs5c62 4.2 adjustment of oscillation frequencies s e l e c t c r y s t a l o s c i l l a t o r s s e l e c t c g a n d c d * 1 * 3 y e s y e s n o n o * 3 * 2 * 4 e n d f i x c g a n d c d < u n l e s s a d j u s t m e n t n e e d s t o b e m a d e t o o s c i l l a t i o n f r e q u e n c i e s : > < i f a d j u s t m e n t n e e d s t o b e m a d e t o o s c i l l a t i o n f r e q u e n c i e s : > r e p l a c e c g w i t h t r i m m e r c a p a c i t o r o p t i m i z e c g a n d c d e n d o p t i m i z e c d c h a n g e r a n k i n g o f o s c i l l a t i o n f r e q u e n c i e s c h a n g e r a n k i n g o f o s c i l l a t i o n f r e q u e n c i e s f i x t r i m m e r c a p a c i t o r m a k e f i n e a d j u s t m e n t t o o s c i l l a t i o n f r e q u e n c i e s * 1) in selecting crystal oscillators, inquire of their suppliers. check how the selected crystal oscillators match the rp/rf/ rs 5c62 and determine the ranking of oscillation frequencies (load capacitance (c l ) in general and equivalent series resistance (r1).) * 2) the oscillatory capacitor c d can be replaced with a trimmer capacitor to adjust oscillation frequencies. * 3) optimize the oscillatory capacitors c g and c d to adjust oscillation frequencies to desired values (on the actual pcb in consideration of possible influ - ences by floating capacitance). note that the greater capacitance of the oscillatory capacitors c g and c d tend to result in increased current con - sumption and prolonged oscillation start time. as a guide, their recommendable capacitance ranges from 5 pf to 20 pf (10 pf to 10-odd pf in par - ticular). (see the typical characteristic measurement.) * 4) set the rotational angle of the trimmer capacitor slightly below the central value in its adjustment range (to ensure matc hing between the central val - ues of the rotational angle and oscillation frequencies in consideration of the fact that smaller capacitance lead to greater f requency variations). oscillation frequencies are subject to variations due to possible fluctuations in ambient temperature and supply voltage (se e typical characteristics?. reference a 32khz crystal oscillator causes a clock delay above or below the central temperature range of 20?c to 25?c. it is therefore recommended to adjust or set oscillation frequencies in such a manner as to become slightly high in room temperature.
22 rp/rf/rs5c62 5. interrupts interrupts are available in the following two types: 1) alarm interrupt: requested upon driving low (turning on) the intr pin in matching between preset alarm time (in minutes and hours) and time indicated by the time counter (in minutes and hours). 2) cyclic interrupt: requested upon driving low (turning on) the intr pin with a preset cycle. to output an alarm interrupt and a cyclic interrupt, the intr pin is configured as shown in the figure below: * 1) when an alarm interrupt and a cyclic interrupt are generated in combination, their logical sum (or) is output from the intr pin. in this event, they can be distinguished from each other by reading the alfg and ctfg bits of the control register 2. * 2) the intr pin output has indefinite states at power-on from 0v. * 3) an alarm interrupt and a cyclic interrupt are both enabled whether the ce pin input is held high or low. * 1) the above figure assumes that an alarm interrupt occurs in the absence of a cyclic interrupt. * 2) the alfg bit has an inverse logic from that of the intr pin output. i n t r a l a r m i n t e r r u p t c y c l i c i n t e r r u p t 5.1 alarm interrupt desired alarm time (in minutes and hours) can be preset in the alarm digits of the alarm register with the alen bit set to ??and then to ??in the control register 1. upon matching between the preset alarm time and the time indicated by the time counter, the intr pin is driven low (turned on) to output a request for an alarm interrupt. the intr pin output can be controlled by using the alen bit in the control register 1 and the alfg bit in the con - trol register 2. a l e n = 1 a l e n = 1 a l e n = 0 a l f g = 0 a l e n = 1 a l e n = 0 a l a r m t i m e m a t c h a l a r m t i m e m a t c h a l a r m t i m e m a t c h a l a r m t i m e m a t c h i n t r m a x . 6 1 . 1 s i n t r a l a r m t i m e m a t c h p e r i o d : 1 m i n u t e alarm-time ................ alarm register (see 2. 6 alarm register .) alen bi (see ?. 1 control register 1?) alfg bit (see ?. 2 control register 2?) cyclic ....................... cyclic interrupt select register (see ?. 5 control register 2?) ctfg bit (see ?. 2 control register 2?) interrupt registers
23 rp/rf/rs5c62 interrupt cycle selection register (see ?.5 interrupt cycle selection register? ctfg bit (see ?.2 control register 2? 5.2 cyc lic interrupt a desired interrupt cycle can be preset in the bits in the interrupt cycle selection register. with the preset inter - rupt cycle, the intr pin is driven low (turned on) to output an request for a cyclic interrupt. a cyclic interrupt can be output from the intr pin in the pulse mode and the level mode. in the level mode in particular, a cyclic interrupt can be disabled by setting the ctfg bit to ??in the control register 2. available interrupt cycles: 6 types (0.488ms, 0.977ms, 7.813ms, 62.5ms, 1s, and 60s) available output modes: 2 types (pulse mode and level mode) c t f g p r e s e t i n t e r r u p t c y c l e i n t r c t f g i n t r i n t e r r u p t s e t t i n g t h e c t f g b i t t o 0 ( i n t e r r u p t ) * 1) a preset interrupt cycle can be canceled by setting the bits to ??in the interrupt cycle selection register. * 2) the above figure assumes that a cyclic interrupt occurs in the absence of an alarm interrupt. * 3) the ctfg bit has an inverse logic from that of the intr pin output. * 1) the timer is stopped upon driving low the ce pin input, but restarted upon driving high the ce pin input. * 2) timer output is disabled upon resetting the tm 3 bit to ??when the stop of oscillation is detected. * 3) the t3 to t1 bits are described in ?. 9 timer clock selection register? * 4) timer output is turned off upon setting the tmr bit to ??in the control register 1 during timer output. cyclic interrupt 6. timer upon lapse of time preset in the timer clock selection register, cyclic pulses are output from the tmout pin. the timer counter can be reset conditional on restart by setting the tmr bit to ??in the control register 1. (it can act as a watchdog timer.) t m o u t t m f g s e t t i n g t h e t m r b i t t o 1 s e t t i n g t h e t m r b i t t o 1 0 . 2 4 4 m s m a x . t 1 t 2 t 3 ?pulse mode (the ct 3 bit is set to ??) (the ctfg bit is not intended for write operation.) ?level mode (the ct 3 bit is set to ??) (the ctfg bit is intended for setting to ??only.)
24 rp/rf/rs5c62 timer clock selection register and tmfg bit (see ?.9 timer clock selection register? tmr bit (see ?.1 control register 1? elements involved in timer reference considerations in using xstp bit 7. detection of stop of oscillation the stop of oscillation can be detected by monitoring the xstp bit in the control register 2. namely, the xstp bit is switched from ??to ??upon detection of the stop of oscillation. this principle can be used to check the valid - ity of time data. (the stop of oscillation can also be detected by using the software-controlled processes described in 11.1.2 initialization subject to setting of xstp bit. ?nitialization at power-o n ?) p o w e r - o n f r o m 0 v * 1 x s t p s t o p o f o s c i l l a t i o n s e t t i n g t h e x s t p b i t t o 0 ( d u r i n g o s c i l l a t i o n ) r e s t a r t o f o s c i l l a t i o n * 2 * 1) the xstp bit is set to ?? at power-on from 0v. note that the xstp bit may be locked at instantaneous power disconnectio n. * 2) once the stop of oscillation has been detected, the xstp bit is kept at ??even after the restart of oscillation. it is recommended to update the settings of the timer clock selection register at regular time intervals to improve the stability of timer operation. ensure error-free detection of the stop of oscillation by: 1) preventing the vdd pin input from making instantaneous power disconnection. 2) preventing the crystal oscillators causing condensation. 3) preventing the crystal oscillators from causing noises on the pcb. 4) preventing the individual pins from being impressed with voltage exceeding the maximum rating.
25 rp/rf/rs5c62 8. t ypical p o wer suppl y cir cuit o s c i n o s c o u t v d d v s s r p / r f / r s 5 c 6 2 v o l t a g e o f s y s t e m p o w e r s u p p l y a b i n t r 1) connect either one end of the oscillatory capacitors c g and c d to the vdd pin. 2) install the by-pass capacitors for both high and low fre - quencies in close proximity to the ic in such a manner as to form a parallel arrangement. 3) connect the pull-up resistor of the intr pin to differ - ent points depending on whether it is used while the ce pin is held low (in battery backup). (i) connect the pull-up resistor to point a in the left circuit diagram unless it is used while the ce pin is held low. (ii) connect the pull-up resistor to point b in the left circuit diagram if it is used while the ce pin is held low.
26 rp/rf/rs5c62 9. t ypical connection between rp/rf/rs5c62 and cpu z 8 0 a 4 t o a 1 5 a 3 t o a 0 d 3 t o d 0 r p / r f / r s 5 c 6 2 a d d r e s s d e c o d e r p o w e r d o w n d e t e c t o r i o r q r d w r a 3 t o a 0 d 3 t o d 0 c s r d w r c e 6 8 0 9 a 4 t o a 1 5 a 3 t o a 0 d 3 t o d 0 r p / r f / r s 5 c 6 2 a d d r e s s d e c o d e r p o w e r d o w n d e t e c t o r b s b a r / w e a 3 t o a 0 d 3 t o d 0 c s r d w r c e a d d r e s s d e c o d e r 8 0 8 6 a l e a 0 t o a 1 9 l a t c h a 0 t o a 1 9 a d 0 t o 1 5 r p / r f / r s 5 c 6 2 p o w e r d o w n d e t e c t o r r d w r a 3 t o a 0 d 3 t o d 0 c s b h e b h e r d w r c e 6 8 0 0 0 a 1 t o a 2 3 d 3 t o d 0 r p / r f / r s 5 c 6 2 p o w e r d o w n d e t e c t o r r / w l d s w r b g a 3 t o a 0 d 3 t o d 0 c s r d w r c e a d d r e s s d e c o d e r rp/rf/rs5c62 and cpu z80 rp/rf/rs5c62 and cpu 6809 rp/rf/rs5c62 and cpu 8086 rp/rf/rs5c62 and cpu 68000
27 rp/rf/rs5c62 10. t ypical characteristics 10.3 current consumption vs. vdd 10.1 current consumption vs. cd 10.2 current consumption vs. cg 10.4 current consumption vs. temperature 0 0 1 2 3 4 v d d = 3 v c d ( p f ) 1 0 2 0 3 0 4 0 c u r r e n t c o n s u m p t i o n i d d ( a ) c d = 5 p f c d = 1 0 p f c d = 2 0 p f c d = 3 0 p f c d = 3 9 p f 0 0 1 2 3 4 t o p t = 2 5 ? c c g = c d = 1 0 p f v d d ( v ) 1 2 3 4 6 5 c u r r e n t c o n s u m p t i o n i d d ( a ) 0 0 1 2 3 4 v d d = 3 v c g ( p f ) 1 0 2 0 3 0 4 0 c u r r e n t c o n s u m p t i o n i d d ( a ) c d = 5 p f c d = 1 0 p f c d = 2 0 p f c d = 3 0 p f c d = 3 9 p f 4 0 0 1 2 3 4 v d d = 3 v c g = c d = 1 0 p f t e m p e r a t u r e t o p t ( ? c ) 2 0 0 2 0 4 0 8 0 6 0 c u r r e n t c o n s u m p t i o n i d d ( a ) a o s c i n v d d c g c d x t a l o s c o u t v d d v s s f r e q u e n c y c o u n t e r i n t r c d =10pf, c g =10pf x'tal : rl 2 35k ? topt=25?c input pin : vdd or vss output pin : open
28 rp/rf/rs5c62 10.7 oscillation frequency vs. v dd 10.5 oscillation frequency vs. cg 10.6 oscillation frequency vs. cd 10.8 oscillation frequency vs. temperature 0 1 0 0 4 0 2 0 6 0 8 0 0 2 0 4 0 6 0 8 0 f 0 : c g = c d = 1 0 p f v d d = 3 v c g ( p f ) 1 0 2 0 3 0 4 0 d f / f o ( p p m ) c d = 1 0 p f c d = 2 0 p f c d = 3 0 p f c d = 5 p f 0 e 4 e 3 e 1 e 2 0 1 f 0 : v d d = 4 v c g = c d = 1 0 p f v d d ( v ) 1 2 3 4 6 5 d f / f o ( p p m ) 0 e 1 0 0 e 4 0 e 2 0 e 6 0 e 8 0 0 2 0 4 0 6 0 8 0 f 0 : c g = c d = 1 0 p f v d d = 3 v c d ( p f ) 1 0 2 0 3 0 4 0 d f / f o ( p p m ) c d = 1 0 p f c d = 2 0 p f c d = 3 0 p f c d = 5 p f e 2 0 e 7 0 e 6 0 e 5 0 e 2 0 e 1 0 e 4 0 e 3 0 0 1 0 f 0 : t o p t = 2 2 . 5 ? c v d d = 3 v , c g = c d = 1 0 p f t o p t ( ? c ) 0 2 0 4 0 8 0 6 0 d f / f o ( p p m ) 10.9 oscillation start time vs. c g 10.10 nch open drain output i ds vs.v ds 0 4 0 . 5 1 . 5 1 2 2 . 5 3 v d d = 3 v c g ( p f ) 1 0 2 0 3 0 4 0 o s c i l l a t i o n s t a r t t i m e ( s ) c d = 5 p f c d = 1 0 p f c d = 2 0 p f c d = 3 0 p f c d = 3 9 p f 0 0 5 1 5 1 0 2 0 2 5 3 0 3 5 v d s ( v ) 0 . 5 1 1 . 5 2 i d s ( m a ) v d d = 3 v v d d = 5 v
29 rp/rf/rs5c62 11. t ypical software-contr olled pr ocesses 11.1 initialization at p o wer -on at power-on from 0v, the internal registers and the output pins have indefinite states and therefore require initial - ization. the process of initialization differs as exemplified below depending on whether the xstp bit (oscillation stop detection bit) is set in the control register 2. in the latter typical process of initialization below, the xstp bit is used to check the validity of internal time data and the presence or absence of the initial routine. 11.1-1 initialization subject to no setting of xstp bit s t a r t p o w e r - o n f r o m 0 v t i m e r c l o c k s e l e c t i o n r e g i s t e r i n t e r r u p t c y c l e s e l e c t i o n r e g i s t e r w a i t y e s n o b s y = 0 ? s e t 1 2 - h o u r o r 2 4 - h o u r t i m e s c a l e , t i m e a n d c a l e n d a r c o u n t e r s , i n t e r r u p t c y c l e s , a n d t i m e r o u t p u t c y c l e s c o n t r o l r e g i s t e r 3 f h c o n t r o l r e g i s t e r 1 3 h c o n t r o l r e g i s t e r 2 0 h c o n t r o l r e g i s t e r 1 f h 0 h 0 h * 2 * 1 * 3 * 4 * 5 * 6 * 1) at power-on from 0v, the internal registers and the output pins have indefinite states. * 2) set both the tsta and tstb bits and the wtrst bit to ??in the control register 3 and thereby set the bsy bit to??in the control register 2. * 3) set the wten bit to ??(clock operation disabled), the alen bit to ? and tmr bit to ??( turn off the output pins) and the bank bit to ??in the control register 1. * 4) drive high (turn off) the intr and tmout pin outputs. * 5) check the bsy bit in the control register 2 for the dual purpose of con - firming the absence of a carry and confirming the start of oscillation. this requires additional time to wait for the start of the crystal oscillators. fur - ther, assign a time-out period to exit from the loop for checking the bsy bit. * 6) start both the clock and alarm functions. * 7) this typical process of initialization is applied at power-on from 0v and not required at start-up from the backup battery.
rp/rf/rs5c62 30 11.1-2 initialization subject to setting of xstp bit s t a r t p o w e r - o n f r o m 0 v i n t e r r u p t c y c l e s e l e c t i o n r e g i s t e r w a i t y e s y e s n o b s y = 0 ? s e t 1 2 - h o u r o r 2 4 - h o u r t i m e s c a l e , t i m e a n d c a l e n d a r c o u n t e r s , i n t e r r u p t c y c l e s , a n d t i m e r o u t p u t c y c l e s c o n t r o l r e g i s t e r 3 f h c o n t r o l r e g i s t e r 1 3 h c o n t r o l r e g i s t e r 1 f h 0 h * 2 * 1 * 3 * 4 * 5 c o n t r o l r e g i s t e r 2 0 h * 7 * 6 * 9 * 8 x s t p = 0 ? n o * 1) at power-on from 0v, the internal registers and the output pins have indefinite states. * 2) check the validity of internal time data. in using the xstp bit, ensure error-free detection of the stop of oscilla - tion by: 1) preventing the crystal oscillators causing condensation. 2) preventing the vdd pin input from making instantaneous power dis - connection. 3) preventing the crystal oscillators from causing noises on the pcb (by such means as signal line isolation). 4) preventing the individual pins from being impressed with voltage exceeding the maximum rating. * 3) set both the tsta and tstb bits and the wtrst bit to ??in the control register 3 and thereby set the bsy bit to ??in the control register 2. * 4) set the wten bit to ??(clock operation disabled), the alen bit to ? and tmr bit to ??( turn off the output pins) and the bank bit to ??in the control register 1. * 5) drive high (turn off) the intr pin output. * 6) wait for the start of the crystal oscillators to confirm the start of oscillation as well as the absence of a carry. further, assign a time-out period to exit from the loop for checking the bsy bit. * 7) set the xstp bit to ??in the control register 2. * 8) start both the clock and alarm functions. * 9) this route is applied at start-up from the backup battery when the process of initialization is omitted, assuming no internal time data destruction.
rp/rf/rs5c62 31 11.2 writing to or reading fr om time and calendar counter s 11.2-1 wr iting to or reading from time and calendar counters b y stopping time count oper ation (b y setting wten and chec king bsy bits) s e t 1 2 - o r 2 4 - h o u r t i m e s c a l e w a i t y e s n o b s y = 0 ? w t e n b a n k 0 0 * 1 * 2 * 3 * 5 * 4 w r i t e t o o r r e a d f r o m t i m e a n d c a l e n d a r c o u n t e r s w t e n 1 * 6 * 1) set the 12- or 24-hour time scale once before writing to the time and cal - endar counters (at the time of initialization after power-on from 0v). * 2) set the wten bit to ??in the control register 1 to stop the second and higher-order digits. * 3) when the bsy bit is set to ??in the control register 2, continue reading from the time and calendar counters until it is set to ??or wait for 122.1 s or more. when the bsy bit is set to ?? it is kept at ??until the wten bit is set to ??again in the control register 1. * 4) writing to the 1-year or 10-year counter automatically enables leap year indication. to disable leap year indication, write ?h?(set the lye bit to ??) in the leap year indication register after setting the time and calen - dar counters. note that leap year indication is continued without correc - tion until the year 2099. * 5) when reading from the time and calendar counters, ensure that this route lasts within 1 second. if this route lasts within 1 second, the 1-second digit is incremented by 1 to correct a 1-second carry occurring during read operation upon setting the wten bit to ??again in the control reg - ister 1. note that the 1-second digit is also incremented by 1 to correct more than one 1-second carry while the wten bit is kept at ?? resulting in a clock delay. * 6) restart time count operation. (the wten bit will automatically be set to ??in the control register 1 upon driving low the ce pin.) * 7) when writing to the time and calendar counters, be sure to check the bsy bit in the control register 2 by disabling a carry (by setting the wten bit to ??). writing to the time and calendar counters must be performed in the absence of a carry. in particular, correct writing to the time and calendar counters requires stopping time count operation (by setting that the wten bit to ??in the control register 1) and confirming the absence of a carry (by checking that the bsy bit to ??in the con - trol register 2). on the other hand, reading from the time and calendar counters may be performed by stopping time count operation, generating a cyclic interrupt, or dual reading.
rp/rf/rs5c62 32 11.2-2 reading from time and calendar counters b y gener ating cyclic interr upt y e s n o p r o c e e d t o i n t e r r u p t f r o m o t h e r i c s c t f g = 0 ? o u t p u t c y c l i c i n t e r r u p t f r o m i n t r p i n * 1 c t f g 0 r e a d f r o m t i m e a n d c a l e n d a r c o u n t e r s this typical process of reading from the time and calendar counters is applied on the conditions below: 1) the intr pin is set to the level mode (upon setting the ct 3 to ??in the interrupt cycle selection register). 2) the route marked with * 1?lasts within the time equivalent to a preset cycle minus 30.5 s (for the purpose of preventing occurrence of an error due to a carry during reading from the time and calendar counters). 11.2-3 reading from time and calendar counters b y dual reading y e s n o d u a l r e a d i n g s m a t c h ? * 1 * 2 r e a d 1 - s e c o n d d i g i t r e a d 1 - s e c o n d d i g i t a g a i n r e a d f r o m t h e t i m e a n d c a l e n d a r c o u n t e r s ( s t a r t i n g w i t h a d d r e s s 1 h a n d e n d i n g w i t h a d d r e s s c h ) * 1) a carry from the second digit starts with 1 second via 10 seconds,---and 1 year, and ends with 10 years. consequently, reading from the time and calendar counters must also start with the 10-second digit (at address ?h?) and end with the 10-year digit (at address ?h?). * 2) this route assumes that an error occurs due to a carry during reading from the time and calendar counters. 11.3 writing alarm time to alarm register s w r i t e a l a r m t i m e ( i n m i n u t e s a n d h o u r s ) a l e n b a n k 0 1 a l e n 1 * 1 * 1) non-existent alarm time may be set in the alarm register, provided that an alarm interrupt is disabled. to enable an alarm interrupt, existent alarm time must be set in the alarm register.
rp/rf/rs5c62 33 11.4 adjusting second digit b y 30 seconds b a n k 1 a d j 1 * 1 * 2 * 1) upon setting the adj bit to ??in the adjustment register, the second and lower-order 1 to 8hz dividers are reset conditional on restart. at this time, when the intr pin is held low for output of a cyclic interrupt with a cycle of 1 second or 60 seconds in the pulse mode, the intr pin is turned off with the timing shown below: 11.5 detecting star t of oscillation n o y e s x s t p = 0 * 1 * 2 * 3 w a i t d e t e c t s t a r t o f o s c i l l a t i o n p o w e r - o n f r o m 0 v 0 x s t p * 1) this typical process of detecting the start of oscillation is applied at pow - er-on from 0v. * 2) at power-on from 0v, the xstp bit is set to ??in the control register 2. * 3) note that the start of oscillation normally requires a time period (oscilla - tion start time) on the order of 0.1 to 2 seconds. further, assign a time- out period to exit from loop for checking the xstp bit in the control regis - ter 2. l o f f m a x i m u m o f 2 0 0 s s e t t i n g t h e a d j b i t t o 1 i n t r * 2) adjustment of the second digit by 30 seconds requires a maximum of 122.1 s, during which the bsy bit is kept a t ??in the control register 2. notice in using the xstp bit, ensure error-free detection of the stop of oscillation by: 1) preventing the crystal oscillators causing condensation. 2) preventing the vdd pin input from making instantaneous power disconnection. 3) preventing the crystal oscillators from causing noises on the pcb (by such means as signal line isolation). 4) preventing the individual pins from being impressed with voltage exceeding the maximum rating.
question 1 : what are the causes of failure in adjustment of oscillation frequencies? (subject to use of variable capacitors and adjustment of oscillation frequencies)
category questions and answers question 3 : how many variation factors should be considered? (subject to use of fixed capacitors and no adjustment of oscillation frequencies)
category questions and answers question 4 : why should you avoid connecting either end of the oscillatory capacitors c g and c d to the vss pin instead of the vdd pin?
category questions and answers 2) software question 4 : an attempt to disable an alarm interrupt by setting the alfg bit to ??in the control regis - ter 2 results in holding the intr pin output low. what is the cause of this phenomenon?
category questions and answers question 5 : an attempt to disable a cyclic interrupt by setting the ctfg bit to ??in the control regis - ter 2 results in holding the intr pin output low. what is the cause of this phenomenon?
category questions and answers 3) hardware question 3 : at power-on from 0v, the intr pin is driven low to output interrupts. what is the cause of this phenomenon?
category questions and answers question 5 : is it possible to configure a power switching circuit containing a diode?
question 1 : what is the difference between backup current consumption and standby current con - sumption?
42 rp/rf/rs5c62 p a cka ge dimensions (unit: mm/(inch)) ? RP5C62 (18pin dip) ? rf5c62 (18pin sop) ? rs5c62 (20pin ssop) 0 t o 1 5 ? 2 4 . 8 m a x . 7 . 6 2 t y p . ( 0 . 3 0 0 t y p . ) 2 . 5 4 t y p . ( 0 . 1 0 0 t y p . ) ( 0 . 3 0 0 t y p . ) 1 . 5 t y p . 6 . 6 m a x . m i n . 0 . 5 1 ( 0 . 1 8 5 m a x . ) ( 0 . 1 1 0 m a x . ) ( 0 . 2 5 9 m a x . ) ( 0 . 9 7 6 m a x . ) 1 8 1 0 1 9 0 . 4 6 + 0 . 1 5 0 . 1 ( 0 . 0 1 8 ) + 0 . 0 0 6 0 . 0 0 4 0 . 2 5 + 0 . 1 5 0 . 0 5 ( 0 . 0 1 0 ) + 0 . 0 0 6 0 . 0 0 2 ( 0 . 0 2 0 ) m i n . 4 . 7 m a x . 2 . 8 m i n . 1 1 . 8 4 m a x . 1 . 2 7 t y p . ( 0 . 0 5 0 t y p . ) 0 . 2 0 . 1 ( 0 . 0 0 8 0 . 0 0 1 ) 2 . 3 4 t y p . ( 0 . 0 9 2 t y p ) ( 0 . 4 6 6 m a x . ) 1 0 . 3 1 0 . 3 ( 0 . 4 0 6 0 . 0 1 2 ) 7 . 4 9 t y p . ( 0 . 2 9 5 t y p . ) 1 . 4 t y p . ( 0 . 0 5 6 t y p . ) 0 . 6 6 0 . 2 ( 0 . 0 2 6 0 . 0 0 8 ) 1 0 9 1 8 1 0 . 2 5 + 0 . 1 0 . 0 5 ( 0 . 0 1 0 ) + 0 . 0 0 4 0 . 0 0 2 0 . 4 1 t y p + 0 . 1 0 . 0 5 ( 0 . 0 1 6 t y p ) + 0 . 0 0 1 0 . 0 0 2 0 . 6 5 1 1 0 1 1 2 0 0 . 2 2 0 . 1 0 . 5 0 . 2 0 t o 1 0 ? 1 . 1 5 0 . 1 4 . 4 0 . 2 6 . 4 0 . 3 0 . 1 0 . 1 0 . 1 5 + 0 . 1 0 . 0 5 6 . 5 + 0 . 3 0 . 1 0 . 4 5 m a x . 0 . 1 m 0 . 1
rp/rf/rs5c62 43 t aping specifica tions (unit: mm) ? rf5c62 (18pin sop) e 1 e 2 u s e r d i r e c t i o n o f f e e d . 1 2 0 . 1 1 1 . 0 5 4 . 0 0 . 1 2 . 0 0 . 1 0 . 3 0 . 0 5 3 . 3 5 0 . 1 2 4 0 . 3 1 1 . 5 0 . 1 1 3 . 2 1 . 7 5 0 . 1 1 . 5 5 0 . 0 5 ? rs5c62 (20pin ssop) e 1 e 2 u s e r d i r e c t i o n o f f e e d . 8 . 0 0 . 1 6 . 7 4 . 0 0 . 1 2 . 0 0 . 0 5 0 . 3 0 . 1 2 . 7 m a x . 1 2 . 0 0 . 3 5 . 5 0 . 0 5 6 . 9 1 . 7 5 0 . 1 1 . 5 + 0 . 1 0
ricoh company, ltd. electronic devices division headquarters 13-1, himemuro-cho, ikeda city, osaka 563-8501, japan phone 81-727-53-1111 fax 81-727-53-6011 yokohama office (international sales) 3-2-3, shin-yokohama, kohoku-ku, yokohama city, kanagawa 222-8530, japan phone 81-45-477-1697 fax 81-45-477-1694 ?1695 http://www.ricoh.co.jp/lsi/english/ ricoh corporation electronic devices division san jose office 3001 orchard parkway, san jose, ca 95134-2088, u.s.a. phone 1-408-432-8800 fax 1-408-432-8375

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